1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular to a method of manufacturing a power semiconductor device for use in power converter devices and having electrodes on a front surface and a rear surface thereof with a thickness of the semiconductor device in the range of 80 to 200 μm.
2. Description of the Related Art
An IGBT (an insulated gate bipolar transistor), a type of power semiconductor device, is a one-chip power device that exhibits a high speed switching characteristic and a voltage driving characteristic, which are possessed by a MOSFET (a metal oxide semiconductor field effect transistor), and a low on-voltage characteristic, which is possessed by a bipolar transistor. The application field of IGBTs is expanding from the industry field including general purpose inverters, AC servo devices, uninterrupted power supplies (UPSs), and switching power supplies, to home appliances including microwave ovens, electric rice cookers, and strobes. IGBTs with new chip structures and lower on-voltage have been developed for application devices aiming at low losses and high efficiency.
There are some types of structures of an IGBT including a punch-through type (abbreviated to “PT” type in the following description), a non punch-through type (abbreviated to an “NPT” type in the following description), and a field stop type (abbreviated to an “FS” type in the following description). Except for some special applications, the main stream structure is an n channel type vertical double diffusion structure. Accordingly, this specification describes the main stream structure of the n channel type IGBT. The description is, however, valid for p-channel type IGBTs as well.
A PT type IGBT is formed using an epitaxial substrate in which an n+ buffer layer and an n− active layer are epitaxially grown on a p+ semiconductor substrate. As a result, a semiconductor device for a withstand voltage of 600 V class has a rather large total thickness of 200 to 300 μm including the p+ semiconductor substrate portion, although an active layer is sufficient with a thickness of about 100 μm. In addition, the PT type IGBT is relatively expensive because of the use of an epitaxial substrate.
Accordingly, IGBTs of an NPT type and an FS type have been developed using in place of the epitaxial substrate, an FZ substrate (a floating zone substrate) that is cut out of a semiconductor ingot manufactured by a floating zone method, intending cost reduction of the IGBT. These types of IGBTs have a low dose, shallow p+ collector layer (a low injection p+ collector) formed on the rear surface of the semiconductor device.
FIG. 11 is a sectional view showing a structure of an NPT type IGBT manufactured using an FZ substrate. Referring to FIG. 11, the NPT type IGBT has an active layer of an n− type semiconductor substrate 1, for example. A p+ base region 2 and an n+ emitter region 3 are selectively formed in the front surface layer of the n− semiconductor substrate 1. A gate electrode 5 is formed on the surface of the n− semiconductor substrate 1 through a gate oxide film 4. An emitter electrode 6 is made in contact with the n+ emitter region 3 and the p+ base region 2 and insulated from the gate electrode 5 with an interlayer dielectric film 7. On the rear surface of the n− semiconductor substrate 1, a p+ collector layer 8 and a collector electrode 9 are formed. The emitter electrode 6 and the collector electrode 9 are formed by evaporating or sputtering a metal such as aluminum, for example.
The NPT type IGBT has a total thickness of a substrate much thinner than that of the PT type IGBT. The NPT type IGBT performs high speed switching without lifetime control because a hole injection rate can be controlled. In addition, the NPT type IGBT is less expensive as compared with the PT type IGBT since the NPT type IGBT is manufactured using an FZ substrate in place of the epitaxial substrate.
FIG. 12 is a sectional view showing a structure of an FS type IGBT. As shown in FIG. 12, the front surface structure of the semiconductor substrate is as same as that of the NPT type IGBT shown in FIG. 11. In the rear surface side of the n− semiconductor substrate 1, an n buffer layer 10 is provided between the n− semiconductor substrate 1 and the p+collector layer 8. The FS type IGBT has a total thickness of the substrate of 80 to 200 μm owing to use of an FZ substrate. Because of depletion in the active layer of n− semiconductor substrate 1 like in the PT type IGBT, a thickness of the n− type semiconductor substrate 1 is about 100 μm for a semiconductor device of a withstand voltage of 600 V. Lifetime control is unnecessary like in the NPT type IGBT. Recently, in order to further reduce the on-voltage, a type of IGBT has been proposed having a structure in which the FS type structure is combined with a trench structure having a narrow and deep groove formed in the surface region of the chip and a MOSFET structure formed in the side region of the groove.
A method of manufacturing the semiconductor device as described above has been disclosed in Japanese Unexamined Patent Application Publication No. 2007-036211, for example, as follows. A front surface structure of a semiconductor element is formed in the first major surface region of a silicon substrate. After reducing the thickness of the substrate by grinding the second major surface, a buffer layer and a collector layer are formed on the second principal surface side. Then on the surface of the collector layer, an aluminum-silicon film is formed having a thickness in the range of 0.3 μm to 1.0 μm with a silicon concentration in the range of 0.5 wt % to 2.0 wt %, preferably not larger than 1.0 wt %. Following formation of the aluminum-silicon film, a collector electrode is formed by depositing a plurality of metal films of titanium, nickel, and gold by means of evaporation or sputtering. The titanium film, the nickel film, and the gold film are a buffer metal film, a soldering metal film, and a protective metal film, respectively.
A rear surface electrode such as a collector electrode is joined using a solder in packaging a semiconductor device. A front surface electrode such as an emitter electrode, on the other hand, is joined mostly employing a wire bonding technique using aluminum wires. Recently, however, the front surface electrode is occasionally joined also by means of soldering. Employment of the soldering for joining the front surface electrode achieves great deal of improvement in high density packaging, high current density, wiring capacitance reduction for high switching speed, and high cooling efficiency of the semiconductor device.
Japanese Unexamined Patent Application Publication No. 2002-110893 discloses a semiconductor device packaged by means of soldering as follows. An E heat sink is bonded with a solder to the front surface of the semiconductor chips. A second conductor member is bonded to the rear surfaces of the semiconductor chips with a solder, and a third conductor member is bonded to the front surface of the E heat sink with a solder. The E heat sink is provided with a step part to form a thin part. The bonding area between the E heat sink and the third conductor member is smaller than the one between the E heat sink and the semiconductor chips. The respective members are sealed with a resin so that the rear surface of the second conductor member and the front surface of the third conductor member are exposed.
A semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2003-110064 comprises a semiconductor element, a first metallic body joined to the rear surface of the semiconductor element and functioning as an electrode and a heat removal member, a second metallic body joined to the front surface of the semiconductor element and functioning as an electrode and a heat removal member, and a third metallic body joined between the front surface of the semiconductor element and the second metallic body. Almost entire semiconductor device is molded with a resin. The thickness of the semiconductor element is made thin so as to reduce the shear stress on the surface of the semiconductor element or to decrease strain component in the joining layers between the semiconductor element and the metallic bodies. The whole semiconductor device is restrained and held with the mould resin. The joining layers are composed of a tin-based solder.
In an actual process of soldering on the front surface electrode, the surface of the front surface electrode needs to be plated with nickel, for example. Commonly employed plating methods are an electroplating method and an electroless plating method. In the electroplating method, metallic ions in the solution are reduced and precipitated by supplying an external electric current. In the electroless plating method, on the other hand, the metallic ions in the solution are chemically reduced and precipitated without using electricity. Consequently, the plating process by means of the electroless plating method can be conducted by a simpler manufacturing apparatus and in a simpler manufacturing process than the electroplating method, which needs an electric circuit including a counter electrode and a dc power supply.
Japanese Unexamined Patent Application Publication No. 2003-096573 discloses a plating process for plating on an electrode surface by means of an electroless plating method, as follows. The method for forming an electroless plated film on pad electrodes of a semiconductor substrate comprises a step of selectively activating the pad electrodes, and a step of immersing the semiconductor substrate in an electroless plating solution and simultaneously precipitating an electroless plated film while supplying a voltage on the semiconductor substrate by an external power supply. The step for activating is either one of a catalyst adding method or a zinc immersion process.
Japanese Unexamined Patent Application Publication No. 2007-019412 discloses another method. An interlayer dielectric film is provided on a semiconductor substrate in which a semiconductor element is formed. A plurality of recessed parts are provided on the surface of a first front surface electrode formed on the interlayer dielectric film corresponding to the configuration of contact holes. The surface of a first rear surface electrode is made uneven by an etching process. As a result, the difference between the surface area of the first front surface electrode and the surface area of the first rear surface electrode is made small. A second front surface electrode and a second rear surface electrode are simultaneously formed on the first front surface electrode and the first rear surface electrode, respectively, by means of a wet plating method. Specifically, the front and rear surfaces of the wafer are simultaneously plated with nickel. Through this process, the second front surface electrode is formed on the front surface side of the wafer and the second rear surface electrode is formed on the rear surface side of the wafer. Then, plated layers are formed simultaneously on the front and rear surfaces of the wafer by means of a wet plating method. Thus, plated layers of gold, for example, are formed on the surface of the second front surface electrode and on the surface of the second rear surface electrode.
In the electroless plating process on the front surface electrode, the surface of the front surface electrode needs to be activated to enhance adhesiveness between the front surface electrode and the plated film because a passive film is formed on the surface of the aluminum electrode and it is difficult to form a plated film having high adhesiveness. A zincate process is known as a method for improving adhesiveness between the front surface electrode and the plated film (see, for example, Japanese Unexamined Patent Application Publication No. 2003-096573 and Japanese Unexamined Patent Application Publication No. 2003-013246).
The following describes a process of plating including the zincating process as a pre-treatment for an electroless plating process. FIG. 13 is a flow chart showing a plating process in a conventional method of manufacturing a semiconductor device. This plating process is conducted on the surface of a front surface electrode composed of an aluminum alloy, for example. A sodium phosphinate (sodium hypophosphite), for example, is used for a reducing agent of a plating bath. First, a degreasing treatment, a step S21, is conducted as shown in FIG. 13. The step 21 removes oil, fat, and foreign matter adhered on the surface of the front surface electrode. At the same time, the step 21 improves wettability of an etching solution for the following step with the surface of the front surface electrode. The degreasing treatment generally uses an alkali solution. An example of the alkali solution can be, for example, a solution containing 20 to 30 g/dm3 of sodium hydroxide (NaOH), 20 to 30 g/dm3 of sodium carbonate (Na2CO3), 20 to 30 g/dm3 of trisodium phosphate (Na3PO4), and 1 to 2 g/dm3 of surfactant (NaOH).
Then, an etching treatment is conducted in step S22 using an acidic solution or an alkaline solution. The step S22 removes a natural oxide film on the surface of the front surface electrode. Then, in step S23, acid cleaning is conducted using nitric acid (HNO3). The step S23 removes impurities (debris) in the surface of the front surface electrode generated in the preceding step of the etching process. Then, in step S24, a first zincate process is conducted. The step 24 substitutes zinc for the aluminum on the front surface electrode, producing a zinc film on the surface of the front surface electrode. Then, in step S25, acid cleaning is conducted using nitric acid. The step S25 removes the zinc film formed on the surface of the front surface electrode. Then, in step S26, a second zincate process is conducted. The step S26 produces again a zinc film on the surface of the front surface electrode.
Then, in step S27, a nickel plated film is formed by an electroless plating process. In the step S27, a mild substitution reaction occurs between the nickel ions in the electroless plating bath and the zinc film on the surface of the front surface electrode. A nickel plated film is formed on the surface of the front surface electrode by an oxidation-reduction reaction between the nickel ions in the plating bath and the reducing agent of sodium hypophosphite. A formula of the oxidation-reduction reaction in this process will be described afterwards. Then, in step S28, a substituted gold film is formed by an electroless plating process. In step S28, a substituted gold plated film is formed on the surface of the nickel plated film by reduction reaction of nickel of the nickel plated film and gold ions in the substituting gold plating bath. In the plating procedure shown in FIG. 13, a washing process with water on the surface of the front surface electrode intervenes between a step and a subsequent step.
In the case using sodium hypophosphite for a reducing agent, the reaction formulas of the electroless nickel plating of step S27 are represented by the following formulas (1), (2) and (3).H2PO2−+H2O→H2PO3−+2H++2e−  (1)Ni2++2e−→Ni  (2)H2PO2−+2H++e−→2H2O+P  (3)
Formula (1) represents an oxidation reaction of the reducing agent. Formula (2) represents a reduction reaction of the nickel ions in the plating bath. Formula (3) represents a reaction that precipitates phosphorus that occurs simultaneously with the reaction of Formula (2).
However, through extensive research made by the inventors of the present invention, it has been found anew that the plated film formed by the plating procedure of FIG. 13 may cause performance variations in the semiconductor devices. One of the reasons for these performance variations of the semiconductor devices can be attributed to a phenomenon in which a hole (also referred to as a etch pit in the following description) reaching the surface of the semiconductor substrate 1 is formed in a part of the emitter electrode 6 by dissolution of aluminum in the emitter electrode 6.
FIG. 14 is a sectional view illustrating a front surface electrode in a normal state in a conventional method of manufacturing a semiconductor device, and FIG. 15 is a sectional view illustrating a front surface electrode in an abnormal state in a conventional method of manufacturing a semiconductor device. A semiconductor device manufactured through a normally conducted plating process as shown in FIG. 14 has a nickel plated film 11 and a substituted gold film (omitted in the figure) successively deposited on the surface of the emitter electrode 6. The other structures are the same as those of the semiconductor device shown in FIG. 12. Thus, the nickel plated film 11 is formed on the emitter electrode 6 and not in contact with the semiconductor substrate 1.
In contrast, when a etch pit 20 is generated in the emitter electrode 6 as shown in FIG. 15, the nickel plated film 11 comes in contact with the semiconductor substrate 1. The etch pit 20 can be presumed to be generated in the etching process (step S23 in FIG. 13) on the emitter electrode 6 after removing a surface oxide film, the etching process being a pre-treatment for the electroless plating process (step S27 in FIG. 13). The etch pit 20 may be also produced in the zincate process (step S24 to step S26 in FIG. 13) on the surface of the emitter electrode 6.
A description is first made about the emitter electrode 6 made by the etching process after removing the surface oxide film. Aluminum, the major component of the emitter electrode 6, has generally a surface oxide film exhibiting excellent corrosion resistance. The surface oxide film exhibits firm corrosion resistance against acid and alkali. When the surface oxide film is removed, the surface of the emitter electrode 6 becomes in a condition with extremely poor corrosion resistance against acid and alkali. When an etching process is conducted in that condition on the surface of the emitter electrode 6 using acid or alkali, the etching proceeds very fast. In addition, the speed of etching process differs depending on the crystal orientation. Etching on the (111) plane of the emitter electrode 6 proceeds faster than on the (110) plane and (100) plane of the emitter electrode 6. Consequently, at some spots on the surface of the electrode 6, the etching proceeds much faster than other places. This difference in etching speed can form recessed spots reaching the surface of the semiconductor substrate 1 in the emitter electrode 6. Thus, the etch pit 20 is generated in the emitter electrode 6.
Next, a description is made about an emitter electrode 6 undergone by the zincate process. Takeshi Nakata et al. report, in the article entitled “Zincate Treatment and Electroless Ni—P Plating on Al Single Crystal Surface” in the journal “Hyoumen Gijutu” (Surface Technology) Vol. 48, No. 8, p. 820-825 (1997), that the precipitation density of zinc on the aluminum surface in the zincate process of aluminum is higher on the (111) plane of aluminum than on (100) plane and (110) plane of aluminum. So, in substitution of zinc for aluminum in (100) plane and (110) plane, precipitation of zinc cannot follow the fast dissolution of aluminum. An emitter electrode 6 with a major component of aluminum involves a possibility that zinc does not precipitate on the surface of the emitter electrode 6 and local etching of aluminum progresses. In this way, an etch pit 20 is generated in the emitter electrode 6.
When an electroless plating process is conducted on a semiconductor device when the electrode 6 has an etch pit generated therein as shown in FIG. 15, the nickel plated film 11 comes in contact with the semiconductor substrate 1 at the etch pit 20. A common electroless plating bath contains an alkali metal such as sodium. The alkali metal may remain at the interface between the nickel plated film 11 and the semiconductor substrate 1 in a semiconductor device having an etch pit 20. The alkali metal remained at the interface between the nickel plated film 11 and the semiconductor substrate 1 diffuses to the gate oxide film 4 in a heat treatment, such as soldering in the packaging process of a semiconductor device, varying the characteristics of the semiconductor device.